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1 hiflex tm ethernet network clock generator pi6lc4820 features ? ? 3.3v supply voltage ? ? crystal input: 25 mhz ? ? diferential input: 25mhz, 156.25 mhz ? ? output frequencies of 312.5, 156.25, 125mhz supported ? ? 9 lvpecl or lvds bank selectable outputs ? ? low 1ps max integrated phase noise design (12khz to 20mhz) ? ? optional xtal or clock input selection ? ? pll bypass mode for test ? ? power supply noise rejection: -50 dbc typical @ 156.25 mhz ? ? packaging (pb-free & green): 48-lead 77mm tqfn description te pi6lc4820 is an lc vco based low phase noise design intended for 10gbe applications. typical 10gbe usage assumes a 25mhz crystal input, while the pll loop is used to generate the 156.25mhz outputs. an additional bufered crystal oscilla - tor output is provided to serve as a low noise reference for other circuitry. for ethernet applications other than 10gbe, programmable dividers allow for simultaneous output of 312.5, 156.25, and 125mhz. pin confguration 1 2 10 9 8 7 6 5 4 3 2019181716151413 36 35 27 28 29 30 31 32 33 34 4142434445464748 v dd_qa qa0+ qa4+ qa3- qa3+ qa2- qa2+ qa1- qa1+ qa0- fs0 x1 v dda qc_mode fs1 gnd pll_byps in_sel v dd_osc x2 in_se in+ qb1+ qb2- qb2+ qa_mode0 qb_mode in- gnd fs_b v dd qa_mode1 fs_c gnd fs_a gnd 12 11 25 26 v dd_pll gnd 24232221 37383940 gnd qc- v dd_qc qc+ v dd_qa qa4- v dd_qb qb0- qb0+ qb1- gnd pi6lc4820 rev d 11/13/13 13-0167
2 block diagram fs1 fs_b v dd n pfd c ha rge/ v dd_pll fs_a m fs0 a pll_byps 1 0/nc 1 0/nc por qa 4+ qa 4- qb0+ qb0- qb1+ qb1- v dd_ qa c fs_c qc+ qc- x1 x2 crystal osci ll ator diff. in+ in- in_sel cmos 0 nc 1 qa 0+ qa 0- qa 1+ qa 1- qa 2+ qa 2- qa 3+ qa 3- b 1 0 qa_mode0 qc_ mode qb_ mode in_se qb2+ qb2- nc v dd _qb qa_mode1 v dd_ qc lc_v co a 1 1 c b 1 0 v dd _ qc nc v dd_osc f_v co saronix-ecera gc25000-76b pi6lc4820 rev d 11/13/13 pi6lc4820 hiflex tm ethernet network clock generator 13-0167
3 pin description pin number pin name type description 1 fs0 input (lvcmos) frequency select pin. use fs0=fs1=0 for all 25mhz input sources. internal pull-down is 100k-ohm 2 x1 input crystal input pin. no internal xtal load capacitance 3 x2 output crystal output pin. no internal xtal load capacitance 4 v dd _ osc power v dd for reference oscillator 5 in_sel input (lvcmos) input mux selection pin 6 pll_byps input (lvcmos) optional mode to bypass pll and have input reference source connect directly to outputs 7 gnd power ground pin 8 fs1 input (lvcmos) frequency select pin. use fs0=fs1=0 for all 25mhz input sources. internal pull-down is 100k-ohm 9 qc_mode input (lvcmos) out mode control pin selects lvpecl or lvds mode. if lef foating, outputs are tri-stated 10 v dda power v dd for analog circuitry 11 gnd power ground pin 12 v dd _ pll power v dd for pll. 13 gnd power ground pin 14 fs_b input (lvcmos) frequency select pin for bank b , output divider 15 gnd power ground pin 16 fs_a input (lvcmos) frequency select pin for bank a , output divider 17 gnd power ground pin 18 fs_c input (lvcmos) frequency select pin for bank c , output divider 19 qa_mode1 input (lvcmos) out mode control pin selects lvpecl or lvds mode. if lef foating, outputs are tri-stated 20 v dd power v dd 21 gnd power ground pin 22, 23 qc-, qc+ output (diferential) bank c lvds/lvpecl selectable output. controlled by qc_mode pin 24 v dd _ qc power v dd for bank c outputs 25 v dd _ qa power v dd for bank a outputs 26, 27 qa4-, qa4+ output (diferential) bank a lvds/lvpecl selectable output. controlled by qa_mode1 pin 28, 29 qa3-, qa3+ output (diferential) bank a lvds/lvpecl selectable output. controlled by qa_mode1 pin 30, 31 qa2-, qa2+ output (diferential) bank a lvds/lvpecl selectable output. controlled by qa_mode0 pin pi6lc4820 rev d 11/13/13 pi6lc4820 hiflex tm ethernet network clock generator 13-0167
4 input mux selection in_sel input 0 select crystal input (pins 2, 3) 1 select in+, in- diferential input (pins 46, 47) nc select in_se lvcmos input (pin 48) pll bypass control function pll_byps pll operation 0 pll enabled 1 pll bypassed nc pll enabled for banks a, b; bank c is driven directly by the output of the input mux. pin number pin name type description 32, 33 qa1-, qa1+ output (diferential) bank a lvds/lvpecl selectable output. controlled by qa_mode0 pin 34, 35 qa0-, qa0+ output (diferential) bank a lvds/lvpecl selectable output. controlled by qa_mode0 pin 36 v dd _ qa power v dd for bank a outputs 37 v dd _ qb power v dd for bank b outputs 38, 39 qb0-, qb0+ output (diferential) bank b lvds/lvpecl selectable output. controlled by qb_mode pin 40, 41 qb1-, qb1+ output (diferential) bank b lvds/lvpecl selectable output. controlled by qb_mode pin 42, 43 qb2-, qb2+ output (diferential) bank b lvds/lvpecl selectable output. controlled by qb_mode pin 44, 45 qa_mode0, qb_mode input (lvcmos) out mode control pins select lvpecl, lvds mode. if lef foating, outputs are tri-stated 46 in- input (diferential) frequency input pin, diferential (accepts: lvds, lvpecl, hcsl) 47 in+ input (diferential) frequency input pin, diferential (accepts: lvds, lvpecl, hcsl) 48 in_se input frequency input pin, single ended input divider control table fs0 divider ratio 0 1 1 5 pin description (continued..) pi6lc4820 rev d 11/13/13 pi6lc4820 hiflex tm ethernet network clock generator 13-0167
5 bank a output control qa_mode0 qa[2:0] qa_mode1 qa[4:3] 0 lvds 0 lvds 1 lvpecl 1 lvpecl nc hi-z nc hi-z bank b output control qb_mode qb[2:0] 0 lvds 1 lvpecl nc hi-z c-bank output interface control confguration qc_mode qc+/- 0 lvds 1 lvpecl nc hi-z output frequency control table fs_a fs_b fs_c output frequency 0 0 0 156.25 1 1 1 125 nc nc nc 312.5 pll feedback divider control table fs1 feedback divider ratio 0 25 1 20 pi6lc4820 rev d 11/13/13 pi6lc4820 hiflex tm ethernet network clock generator 13-0167
6 operating conditions symbol parameters min. max. units v dd general power supply voltage 3.0 3.6 v t a ambient temperature C40 85 c i dd power supply current all outputs loaded 425 ma i dd _ a power supply current for pin10 13 i dd _ pll power supply current for pin12 30 v dda analog power supply voltage 2.7 3.6 v v dd _ pll pll power supply voltage 2.7 3.6 lvcmos input electrical characteristics symbol parameters conditions min. ty p. max. units v ih input high voltage fs0, fs1 2 v v il input low voltage 0.8 v v ih input high current in_sel, pll_byps, fs_a, fs_b, fs_c, qa_mode, qb_mode, qc_mode 2.6 v v il input low current 0.8 v i ih input high current v in = v dd 45 m a i il input low current v in = 0v -45 m a r pu internal pull up resistance 100 k w r dn internal pull down resistance 100 k w t dc input duty cycle 35 65 % c in input capacitance 1 1.5 pf f in input frequency 15 160 mhz note: 1. tere is no internal load capacitance built in to the x1 and x2 pins storage temperature .......................................................... C65c to +150c supply voltage to ground potential, v dd ...................... C0.5v to +4.6v esd protection (hbm) ..................................................................... 2000 v note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. tis is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may afect reliability. maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) pi6lc4820 rev d 11/13/13 pi6lc4820 hiflex tm ethernet network clock generator 13-0167
7 lvpecl output characteristics symbol parameters condition min. ty p. max. units f out output frequency 25 312.5 mhz t rise / t fall rise and fall time 20% to 80%, single- ended 400 ps t dc duty cycle diferential 47 53 % j phase integrated phase jitter 12khz-20mhz @ 156.25mhz, 25mhz xtal input 0.54 1 ps rms t dis output disable time 80 ns t en output enable time 80 ns t lock pll lock time 2 ms v pp output peak-peak voltage single-ended 0.6 1 v v oh output high voltage v dd = 3.3v v dd -1.4 v dd -0.9 v v ol output low voltage v dd = 3.3v v dd -2.0 v dd -1.7 v lvds output characteristics symbol parameters condition min. ty p. max. units f out output frequency 25 312.5 mhz t rise / t fall rise and fall time 20% to 80%, single- ended 270 ps t dc duty cycle diferential 47 53 % j phase integrated phase jitter 12khz-20mhz @ 156.25mhz, 25mhz xtal input 0.54 1 ps rms differential input characteristics symbol parameters conditions min. ty p. max. units v ih input high voltage v dd - 0.7 v v il input low voltage v dd - 2.0 v v cm input bias voltage v dd - 1.8 v dd / 2 v r in input diferential impedence 2 80 100 120 w v in-pp input diferential swing 0.3 1.8 v pp c in diferential input capacitance 1.5 pf note: 1. 2. diferential input can be ac or dc coupled. (over operating conditions. see fig. 1 and 2 for load conditions.) (over operating conditions see fig. 1 and 2 for load conditions.) pi6lc4820 rev d 11/13/13 pi6lc4820 hiflex tm ethernet network clock generator 13-0167
8 crystal characteristic parameters description min ty p max. units oscmode mode of oscillation fundamental freq frequency 25 mhz esr (1) equivalent series resistance 50 ohm cload load capacitance 18 pf cshunt shunt capacitance 7 pf drive level 0.1 mw note: 1. esr value is dependent upon frequency of oscillation power supply noise rejection specifcation parameter conditions min. typ max. units supply noise induced phase spur @ 156.25 nhz output (see note) fm = 100khz to 400khz -50 dbc note: 1. measured with 50mvp-p sinusoidal interference on the supply vddqx, measured with the supply flter as shown in figure 2. symbol parameters condition min. ty p. max. units t dis output disable time 80 ns t en output enable time 80 t lock pll lock time 2 ms |v amp | 1 diferential output voltage ampli - tude |v oh - v ol | with 100f external ter - mination 250 520 mv |v oh - v ol | with 120f external ter - mination 250 600 v oh output high voltage 1.8 v v ol output low voltage 0.925 v os output ofset voltage 1.125 1.375 r ol diferential output impedance 85 140 ? note: 1. valid for part numbers with date code afer y1338. lvds output characteristics (continued..) (link to "http://www.pericom.com/saronix" for more detailed crystal specifcations) pi6lc4820 rev d 11/13/13 pi6lc4820 hiflex tm ethernet network clock generator 13-0167
9 figure 1. test circuit figure 2. power supply filter m 0.1 f 0.1 f 10 f 3.3v 5% 10.5 v ddqx v dda v dd_pll application notes pi6lc4820 is a hih perforance and lo itter clock enerator for advanced giabit ethernet systes. it has three independent banks hose outputs can be set to lvpecl or lvds and in 3 outputs frequencies 125m 156.25m and 312.5m. it is criti - cal to ensure the poer supply is properly decoupled and the layout around the crystal is properly routed to achieve this lo itter perforance. e folloin uide is hihly recoended to be adopted into the syste pcb desins. pi6lc4820 rev d 11/13/13 pi6lc4820 hiflex tm ethernet network clock generator 13-0167
10 power decoupling schematic 1) it is suggested to use the schematics decoupling rc value to get best board noise fltering 2) typical lvpecl is using 150 w pull down in ac or dc coupling drive according to asic ref_clk i/o spec 3) te crystal circuit c1/c2 load values are for cl=18pf crystal, they can be adjusted for other cl crystals 4) please refer to the datasheet for other static i/o logic set for the request work modes and output frequencies r7 4. 7_603 vdd clk_qa2_p clk_qa1_n c10 0.01uf vdd_qa c16 0.1uf fs_0 y1 25m (cl=18p) fs_1 clk_qa0_p clk_qb2_p vdd clk_qc0_n c7 0.1uf c15 22uf r5 150 vdd oa4_p fs_a r2 2. 2_603 qb_mode vdd input_n clk_qa4_p r2 4. 7_603 clk_qb2_n vdd_qb clk_qa0_n c4 1uf vdd clk_qa3_n u1 pi6lc4820 16 44 25 22 34 35 32 33 30 31 26 45 46 36 14 37 9 18 24 47 48 5 38 39 41 42 43 28 19 29 27 8 1 6 2 3 40 23 10 12 20 21 49 17 15 13 11 7 4 fs_a qa_mode0 vdd_qa1 qc0+ qa0- qa0+ qa1- qa1+ qa2- qa2+ qa4- qa_mode in- vdd_qa2 fs_b vdd_qb qc_mode fs_c vdd_qc in+ in_se in_sel qb0- qb0+ qb1+ qb2- qb2+ qa3- qa_mode1 qa3+ qa4+ fs_1 fs_0 pll_by ps x1 x2 qb1- qc0- vdda vdd_pll vdd gnd6 ep gnd5 gnd4 gnd3 gnd2 gnd1 vdd_osc qa4_n r8 2. 2_603 c12 0.1uf in_se clk_qa4_n qa_mode_1 c2 33p c3 2.2uf clk_qb1_n qa_mode_0 c1 27p r3 2. 2_603 clk_qb0_n qc_mode clk_qa1_p c9 0.1uf c8 2.2uf place to pin c6 2.2uf vdd vdd fs_c clk_qb0_p pll_by pass r6 10_802 vdd_qc r4 150 clk_qc0_p c15 22uf r1 2. 2_603 place to pin c14 0.1uf clk_qa2_n place to pin c15 22uf to lvpecl eq. 100 termination c11 0.01uf c5 0.1uf fs_b clk_qb1_p in_select input_p clk_qa3_p pi6lc4820 rev d 11/13/13 pi6lc4820 hiflex tm ethernet network clock generator 13-0167
11 4 copyright pericom semiconductor 2007 last slide pericom confidential information 2. pi6lc4820 crystal circuit layout guide 1 4 3 2 5 6 7 8 1 2 3 4 5 6 7 8 pin name 1 fs0 2 x1 3 x2 4 vdd_osc 5 in_sel 6 pll-bybs 7 gnd 8 fs1 pcb layers: l_1 signal (top) l_2 gnd plane solder pad board via keep out area gnd pad crystal pad c1 cap. pad gnd via crystal circuit oscillator crystal circuit connection te following diagram shows pi6lc4820 crystal circuit connection with a parallel crystal. for the cl=18pf crystal, it is suggested to use c1=27pf, c2=33pf. c1 and c2 can be adjusted to fne tune to the target ppm of crystal oscillator according to diferent board layouts. c1 27pf crystal?(c l? =?18pf) c2 33pf x1 x2 saronix-ecera gc2500076b crystal oscillator circuit recommended crystal specifcation a) gc2500003 xtal 49s/smd(4.0 mm), 25m, cl=18pf, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/gc_gf.pdf b) fy2500081, smd 5x3.2(4p), 25m, cl=18pf, +/-30ppm, http://www.pericom.com/pdf/datasheets/se/fy_f9.pdf c) fl2500047, smd 3.2x2.5(4p), 25m, cl=18pf, +/-20ppm, http://www.pericom.com/pdf/datasheets/se/fl.pdf pi6lc4820 rev d 11/13/13 pi6lc4820 hiflex tm ethernet network clock generator 13-0167
12 6 copyright pericom semiconductor 2007 last slide pericom confidential information 2 . pi6lc4820 crystal circuit layout guide 1 4 3 2 5 6 7 8 1 2 3 4 5 6 7 8 pin name 1 fs0 2 x1 3 x2 4 vdd_osc 5 in_sel 6 pll-bybs 7 gnd 8 fs1 pcb layers: l_1 signal (top) l_2 gnd plane solder pad board via keep out area gnd pad crystal pad c1 cap. pad gnd via gnd via trace l_1 4. vdd and gnd pins layout 1) small value decoupling caps. (0.1uf, 1uf, and 2.2uf) should be placed close to each vdd pin or via 2) each gnd pin should have its own via to the common gnd plane 3) termal pad must be connected to the gnd plane for better thermal distribution and signal conducting with reasonable via counts (>6) 5. lvpecl differential output layout 1) 150 w pull-down should be put close to clock output side with symmetrical position in one pair 2) do not share 150 w pull-down gnd via between each pairs 6. differential input 1) tis device diferential input (pin 47, 48) can accept 25mhz, 125mhz, and 156.25mhz frequencies in most common diferential signals (lvpecl, lvds, hcsl etc.) in either ac or dc coupling, with proper in_sel, fs0, and fs1 setting 2) te device diferential input has equivalent 100 w diferential termination on chip, so pcb 100 w external termination is normally not necessary. crystal layout example 1) x1 pin is the most sensitive as crystal amplifer input 2) x1 and x2 pins connected to crystal trace loop should be very narrow without any board via in the loop and keep the via out of the area 3) place crystal as close to the ic as possible along with c1/c2 load caps. tere should be no via at the top layer to the crystal 4) keep crystal load cap. c1/c2 to gnd sides as close as possible so that the minimum board noise could be coupled into the caps pi6lc4820 rev d 11/13/13 pi6lc4820 hiflex tm ethernet network clock generator 13-0167
13 ordering information (1-3) ordering code package code package description PI6LC4820ZDE zd 48-pin, pb-free & green (tqfn) notes: 1. termal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. e = pb-free and green 3. 3. adding an x sufx = tape/reel pericom semiconductor corporation ? 1-800-435-2336 ? www .pericom.com packaging mechanical: 48-pin tqfn (zd) 1 description: 48-contact, thin fine pitch quad flat no-lead (tqfn) package code: zd (zd48) document control #: pd-2045 revision: e notes: 1. all dimensions are in millimeters, angles are in degrees. 2. refer jedec mo-220/vkkd 3. thermal pad soldering area 4. depending on the method of lead termination at the edge of the package, pull back maybe present. date: 0543/09/12 12-0458 note: 1. ? for latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php pi6lc4820 rev d 11/13/13 pi6lc4820 hiflex tm ethernet network clock generator 13-0167

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